集成电路3D硅集成

T. Chammah, T. Giuma
{"title":"集成电路3D硅集成","authors":"T. Chammah, T. Giuma","doi":"10.1109/ICONS.2009.13","DOIUrl":null,"url":null,"abstract":"One of the most pressing problems in present digital devices are those on-chip and between chips interconnections. Associated with these are the difficulties of placing logic elements as well as routing of their interconnections. As traditional metal-oxide semiconductor field-effect transistor (MOSFET) design and composition are continuously tweaked and scaled to smaller dimensions, interconnect innovation has struggled to keep pace.  This has lead to an increasing performance disparity between transistor switching latency and wire transmission time.  The mismatch has implications for integrated circuit (IC) design resulting in slower, more power hungry and space-inefficient circuits.3D silicon integration is a proposed solution that promises to simultaneously increase chip-level performance and decrease overall power consumption while boosting transistor density and computational power per unit volume.  The implications of this novel approach to integration are assessed through an initial 3D processor test vehicle implementation.","PeriodicalId":270103,"journal":{"name":"2009 Fourth International Conference on Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Integrated Circuits 3D Silicon Integration\",\"authors\":\"T. Chammah, T. Giuma\",\"doi\":\"10.1109/ICONS.2009.13\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"One of the most pressing problems in present digital devices are those on-chip and between chips interconnections. Associated with these are the difficulties of placing logic elements as well as routing of their interconnections. As traditional metal-oxide semiconductor field-effect transistor (MOSFET) design and composition are continuously tweaked and scaled to smaller dimensions, interconnect innovation has struggled to keep pace.  This has lead to an increasing performance disparity between transistor switching latency and wire transmission time.  The mismatch has implications for integrated circuit (IC) design resulting in slower, more power hungry and space-inefficient circuits.3D silicon integration is a proposed solution that promises to simultaneously increase chip-level performance and decrease overall power consumption while boosting transistor density and computational power per unit volume.  The implications of this novel approach to integration are assessed through an initial 3D processor test vehicle implementation.\",\"PeriodicalId\":270103,\"journal\":{\"name\":\"2009 Fourth International Conference on Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Fourth International Conference on Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICONS.2009.13\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Fourth International Conference on Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICONS.2009.13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

当前数字器件中最紧迫的问题之一是片内互连和片间互连。与此相关的是放置逻辑元素以及它们的互连路由的困难。随着传统金属氧化物半导体场效应晶体管(MOSFET)的设计和组成不断调整,并缩小到更小的尺寸,互连创新一直在努力跟上步伐。这导致晶体管开关延迟和导线传输时间之间的性能差距越来越大。这种不匹配对集成电路(IC)设计有影响,导致电路速度较慢,功耗更高,空间效率低。3D硅集成是一种被提议的解决方案,它承诺同时提高芯片级性能和降低总体功耗,同时提高晶体管密度和单位体积的计算能力。通过最初的3D处理器测试车辆实施,评估了这种新型集成方法的含义。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Integrated Circuits 3D Silicon Integration
One of the most pressing problems in present digital devices are those on-chip and between chips interconnections. Associated with these are the difficulties of placing logic elements as well as routing of their interconnections. As traditional metal-oxide semiconductor field-effect transistor (MOSFET) design and composition are continuously tweaked and scaled to smaller dimensions, interconnect innovation has struggled to keep pace.  This has lead to an increasing performance disparity between transistor switching latency and wire transmission time.  The mismatch has implications for integrated circuit (IC) design resulting in slower, more power hungry and space-inefficient circuits.3D silicon integration is a proposed solution that promises to simultaneously increase chip-level performance and decrease overall power consumption while boosting transistor density and computational power per unit volume.  The implications of this novel approach to integration are assessed through an initial 3D processor test vehicle implementation.
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