Toward sub-20nm pitch Fin patterning and integration with DSA

Directed Self Assembly (DSA) has gained increased momentum in recent years as a cost-effective means for extending lithography to sub-30nm pitch, primarily presenting itself as an alternative to mainstream 193i pitch division approaches such as SADP and SAQP. Towards these goals, IMEC has excelled at understanding and implementing directed self-assembly based on PS-b-PMMA block co-polymers (BCPs) using LiNe flow [1]. These efforts increase the understanding of how block copolymers might be implemented as part of HVM compatible DSA integration schemes. In recent contributions, we have proposed and successfully demonstrated two state-of-the-art CMOS process flows which employed DSA based on the PS-b-PMMA, LiNe flow at IMEC (pitch = 28 nm) to form FinFET arrays via both a ‘cut-last’ and ‘cut-first’ approach [2-4]. Therein, we described the relevant film stacks (hard mask and STI stacks) to achieve robust patterning and pattern transfer into IMEC’s FEOL device film stacks. We also described some of the pattern placement and overlay challenges associated with these two strategies. In this contribution, we will present materials and processes for FinFET patterning and integration towards sub-20 nm pitch technology nodes. This presents a noteworthy challenge for DSA using BCPs as the ultimate resolution for PS-b-PMMA may not achieve such dimensions. The emphasis will continue to be towards patterning approaches, wafer alignment strategies, the effects of DSA processing on wafer alignment and overlay.