An all digital 650-Mbps demonstration receiver for NASA's high data rate satellite applications

A demonstration receiver that tracks and demodulates 650-Mb/s QPSK (quadrature phase-shift keying) data has been developed, utilizing a parallel processing VLSI architecture and multirate digital signal processing, to meet upcoming NASA satellite communication requirements. Data rates of 650 Mb/s were achieved with low implementation loss and two-sample/symbol operation using high-speed digital GaAs logic in the front and back end, with the majority of the computationally intensive signal processing implemented in CMOS VLSI. Using a parallel architecture combined with multirate digital signal processing means that receiver speed is no longer limited to the speed of the signal processing hardware elements, but only by the speed of the analog-to-digital converters. In addition to unsurpassed data rate levels, superior bit error rate (BER) performance has been achieved using a joint feedforward and feedback timing estimator and data recovery algorithm. Laboratory performance results for the hardware demonstration receiver are presented as well as a detailed discussion of the hardware implementation and signal processing algorithms.<>