{"title":"超低导通电阻TG-LDMOS，具有三个分离栅极和可与DG-LDMOS媲美的高k介电","authors":"Chen Jia, Xianglong Li, Yabin Sun, Xiaojin Li, Yun Liu, Yanfang Ding, Yanling Shi","doi":"10.1109/icet55676.2022.9825250","DOIUrl":null,"url":null,"abstract":"In this paper, a novel ultralow specific on-resistance (Ron,sp) triple gate lateral double-diffused MOS (TG-LDMOS) and high-k (HK) gate dielectric is proposed which is simulated by TCAD tool. It is the main concern for LDMOS to optimize the trade-off relationship between the Breakdown Voltage (BV) and specific on-resistance (Ron,sp). Adding another vertical gate compared to double gate LDMOS (DG-LDMOS) will increase the route of current, thus decreasing resistance obviously. In addition, the HK gate dielectric can optimize the channel current, which also reduces resistance. It is found that the proposed device shows lower resistance of 30.2m Ω · cm2 (TG-LDMOS) and 25.4 m Ω.cm2(TG-LDMOS(k)) at the same BV=180V. The Ron,sp is 22.3% and 53.1% lower than that of DG-LDMOS, respectively. Compared with DG-LDMOS and TG-LDMOS, the TG-LDMOS(k) achieves better tradeoff between the BV and Ron,sp.","PeriodicalId":166358,"journal":{"name":"2022 IEEE 5th International Conference on Electronics Technology (ICET)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Ultra-Low On-Resistance TG-LDMOS With Three Separated Gates and High-k Dielectric Comparable to DG-LDMOS\",\"authors\":\"Chen Jia, Xianglong Li, Yabin Sun, Xiaojin Li, Yun Liu, Yanfang Ding, Yanling Shi\",\"doi\":\"10.1109/icet55676.2022.9825250\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a novel ultralow specific on-resistance (Ron,sp) triple gate lateral double-diffused MOS (TG-LDMOS) and high-k (HK) gate dielectric is proposed which is simulated by TCAD tool. It is the main concern for LDMOS to optimize the trade-off relationship between the Breakdown Voltage (BV) and specific on-resistance (Ron,sp). Adding another vertical gate compared to double gate LDMOS (DG-LDMOS) will increase the route of current, thus decreasing resistance obviously. In addition, the HK gate dielectric can optimize the channel current, which also reduces resistance. It is found that the proposed device shows lower resistance of 30.2m Ω · cm2 (TG-LDMOS) and 25.4 m Ω.cm2(TG-LDMOS(k)) at the same BV=180V. The Ron,sp is 22.3% and 53.1% lower than that of DG-LDMOS, respectively. Compared with DG-LDMOS and TG-LDMOS, the TG-LDMOS(k) achieves better tradeoff between the BV and Ron,sp.\",\"PeriodicalId\":166358,\"journal\":{\"name\":\"2022 IEEE 5th International Conference on Electronics Technology (ICET)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 5th International Conference on Electronics Technology (ICET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/icet55676.2022.9825250\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 5th International Conference on Electronics Technology (ICET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icet55676.2022.9825250","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文提出了一种新型的超低比导通电阻(Ron,sp)三栅横向双扩散MOS (TG-LDMOS)和高k (HK)栅极介质，并利用TCAD工具进行了仿真。优化击穿电压(BV)和特定导通电阻之间的权衡关系是LDMOS的主要关注点(Ron,sp)。与双栅LDMOS (DG-LDMOS)相比，增加一个垂直栅极将增加电流的路径，从而明显降低电阻。此外，HK栅极介质可以优化通道电流，这也降低了电阻。结果表明，在相同BV=180V时，该器件的电阻分别为30.2m Ω·cm2(TG-LDMOS)和25.4 m Ω.cm2(TG-LDMOS(k))。与DG-LDMOS相比，Ron,sp分别降低22.3%和53.1%。与DG-LDMOS和TG-LDMOS相比，TG-LDMOS(k)在BV和Ron等人之间实现了更好的平衡。
Ultra-Low On-Resistance TG-LDMOS With Three Separated Gates and High-k Dielectric Comparable to DG-LDMOS
In this paper, a novel ultralow specific on-resistance (Ron,sp) triple gate lateral double-diffused MOS (TG-LDMOS) and high-k (HK) gate dielectric is proposed which is simulated by TCAD tool. It is the main concern for LDMOS to optimize the trade-off relationship between the Breakdown Voltage (BV) and specific on-resistance (Ron,sp). Adding another vertical gate compared to double gate LDMOS (DG-LDMOS) will increase the route of current, thus decreasing resistance obviously. In addition, the HK gate dielectric can optimize the channel current, which also reduces resistance. It is found that the proposed device shows lower resistance of 30.2m Ω · cm2 (TG-LDMOS) and 25.4 m Ω.cm2(TG-LDMOS(k)) at the same BV=180V. The Ron,sp is 22.3% and 53.1% lower than that of DG-LDMOS, respectively. Compared with DG-LDMOS and TG-LDMOS, the TG-LDMOS(k) achieves better tradeoff between the BV and Ron,sp.
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