Optimized structure of single photon avalanche diode with low dark count rate

In this paper, an optimized structure of single photon avalanche diode (SPAD) with p-i-n construction is presented, and the device is compatible with standard CMOS technology. TCAD software and accurate calculation method based on physics mechanism are employed for the device structure design and DCR calculation, respectively. The characteristic parameters of the device, such as electric field and electron and hole triggering probability, are available through TCAD Atlas device simulation. The central region of P-sub doping is designed as a part of avalanche region, which achieves a lower electric field, and makes the band-to-band tunneling suppressed simultaneously. The breakdown voltage of the SPAD is 38.5 V. At excess bias voltage of 5 V, DCR is 0.88 Hz/μm2 at room temperature. The maximum electric field of the optimized structure is 3.8×105 V/cm. As for PDE, at room temperature with 5.0 V excess bias, the PDE is greater than 30% in the 400 nm-675 nm range, with a peak PDE of 40% at 550 nm. At 850 nm, there is still a photon detection efficiency of more than 10%, making the SPAD still have a certain detection capability. The superior performance of this structure makes it suitable for wide applications.