S. Pae, H. Sagong, C. Liu, M. Jin, Y. H. Kim, S. Choo, J. J. Kim, H. J. Kim, S. Yoon, H. Nam, H. Shim, S. M. Park, J. Park, S. Shin, J. Park
{"title":"考虑 14 纳米 FinFET 电路老化和产品验证中的物理机制和几何相关性","authors":"S. Pae, H. Sagong, C. Liu, M. Jin, Y. H. Kim, S. Choo, J. J. Kim, H. J. Kim, S. Yoon, H. Nam, H. Shim, S. M. Park, J. Park, S. Shin, J. Park","doi":"10.1109/IEDM.2015.7409744","DOIUrl":null,"url":null,"abstract":"We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.","PeriodicalId":336637,"journal":{"name":"2015 IEEE International Electron Devices Meeting (IEDM)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations\",\"authors\":\"S. Pae, H. Sagong, C. Liu, M. Jin, Y. H. Kim, S. Choo, J. J. Kim, H. J. Kim, S. Yoon, H. Nam, H. Shim, S. M. Park, J. Park, S. Shin, J. Park\",\"doi\":\"10.1109/IEDM.2015.7409744\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.\",\"PeriodicalId\":336637,\"journal\":{\"name\":\"2015 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2015.7409744\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2015.7409744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations
We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.