一个改进的忆阻器- cmos异或逻辑门和一个新的全加法器

Xiaoping Wang, Ran Yang, Qiao Chen, Z. Zeng
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引用次数: 8

摘要

本文提出了一种改进的异或逻辑门和一种新的全加法器。该XOR结构简单,由2个CMOS晶体管和4个忆阻器组成,比以前减少了4个CMOS晶体管。此外,新型全加法器由7个CMOS晶体管和10个忆阻器组成。这种新颖的全加法器减少了8个CMOS晶体管和2个忆阻器,这意味着电路的尺寸更小,功耗更低。通过分析和仿真,验证了改进的异或逻辑门和新型全加法器的可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An improved memristor-CMOS XOR logic gate and a novel full adder
This brief proposes an improved XOR logic gate and a novel full adder. The presented XOR has simple structure which consists of 2 CMOS transistors and 4 memristors, and it reduces 4 CMOS transistors compared with the previous. In addition, the novel full adder consists of 7 CMOS transistors and 10 memristors. This novel full adder reduces 8 CMOS transistors and 2 memristors, which means the size of the circuit is smaller and power consumption is lower. Through analysis and simulation, the feasibilities of the improved XOR logic gate and novel full adder are demonstrated.
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