{"title":"用于25.6 Mbps ATM交换机的4通道模拟前端","authors":"K. Lawrence Loh, S. Narayan, A. Kuo, S. Mohapatra","doi":"10.1109/CICC.1997.606636","DOIUrl":null,"url":null,"abstract":"This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 4-channel analog front end for 25.6 Mbps ATM switches\",\"authors\":\"K. Lawrence Loh, S. Narayan, A. Kuo, S. Mohapatra\",\"doi\":\"10.1109/CICC.1997.606636\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels.\",\"PeriodicalId\":111737,\"journal\":{\"name\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of CICC 97 - Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1997.606636\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606636","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-channel analog front end for 25.6 Mbps ATM switches
This chip integrates four 32 MHz channels for twisted-pair cable digital communication using a 0.5 um digital CMOS process. The implementation features all major analog signal processing blocks on chip with a minimum number of offchip passive components. A PLL is used to provide transmit clocks as well as to center four pairs of gated VCOs for data synchronization. A 1st-order adaptive equalizer is designed to provide proper high-frequency boosting for different lengths of connecting cables. A current-mode filter with direct current amplification is used to provide output pulse shaping to conform 25.6 Mbps ATM output waveform templates. The power dissipation is measured at 1.3 W (325 mW per channel) during full operation of all 4 channels.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
