{"title":"一种高吞吐量、低延迟扩展码解码器的设计","authors":"Pengwei Zhang, F. Lau, Chiu-Wing Sham","doi":"10.23919/APCC.2017.8304002","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.","PeriodicalId":320208,"journal":{"name":"2017 23rd Asia-Pacific Conference on Communications (APCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a high-throughput low-latency extended golay decoder\",\"authors\":\"Pengwei Zhang, F. Lau, Chiu-Wing Sham\",\"doi\":\"10.23919/APCC.2017.8304002\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.\",\"PeriodicalId\":320208,\"journal\":{\"name\":\"2017 23rd Asia-Pacific Conference on Communications (APCC)\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 23rd Asia-Pacific Conference on Communications (APCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/APCC.2017.8304002\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 23rd Asia-Pacific Conference on Communications (APCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/APCC.2017.8304002","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a high-throughput low-latency extended golay decoder
In this paper, we propose a parallel architecture of the imperfect maximum likelihood decoding (IMLD) method, called PIMLD. It is further implemented onto an FPGA and applied to decode the (24,12,8) extended Golay code. Experimental results show that the proposed PIMLD decoder achieves 12.0 Gb/s throughput at 500 MHz frequency. Moreover, the latency for the decoder is only 5 clock cycles.
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