{"title":"90nm CMOS中使用堆叠交叉耦合晶体管的w波段比3注入锁定分频器","authors":"Yo‐Sheng Lin, K. Lan, Yu-Ching Lin","doi":"10.1109/RWS.2019.8714280","DOIUrl":null,"url":null,"abstract":"We demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor (CCT) topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower CCTs and then inject the source terminals of the upper CCTs. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower CCTs. Due to the strong second harmonic signal (2finj) at the source terminals of the upper CCTs, there are notable locked fundamental signals (finj) at the drain terminals of the upper CCTs. ILFD31 consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.","PeriodicalId":131330,"journal":{"name":"2019 IEEE Radio and Wireless Symposium (RWS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"W-Band Divide-by-3 Injection-Locked Frequency Divider Using Stacked Cross-Coupled Transistors in 90 nm CMOS\",\"authors\":\"Yo‐Sheng Lin, K. Lan, Yu-Ching Lin\",\"doi\":\"10.1109/RWS.2019.8714280\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor (CCT) topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower CCTs and then inject the source terminals of the upper CCTs. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower CCTs. Due to the strong second harmonic signal (2finj) at the source terminals of the upper CCTs, there are notable locked fundamental signals (finj) at the drain terminals of the upper CCTs. ILFD31 consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.\",\"PeriodicalId\":131330,\"journal\":{\"name\":\"2019 IEEE Radio and Wireless Symposium (RWS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Radio and Wireless Symposium (RWS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS.2019.8714280\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Radio and Wireless Symposium (RWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2019.8714280","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
W-Band Divide-by-3 Injection-Locked Frequency Divider Using Stacked Cross-Coupled Transistors in 90 nm CMOS
We demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor (CCT) topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower CCTs and then inject the source terminals of the upper CCTs. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower CCTs. Due to the strong second harmonic signal (2finj) at the source terminals of the upper CCTs, there are notable locked fundamental signals (finj) at the drain terminals of the upper CCTs. ILFD31 consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.