90nm CMOS中使用堆叠交叉耦合晶体管的w波段比3注入锁定分频器

Yo‐Sheng Lin, K. Lan, Yu-Ching Lin
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引用次数: 1

摘要

我们展示了两个低功耗和宽锁定范围w波段CMOS除以3注入锁定分频器(ILFD3)使用堆叠交叉耦合晶体管(CCT)拓扑结构。第一个ILFD3 (ILFD31)使用片上平衡器将单输入信号转换为差分输出信号,由下部cct放大,然后注入上部cct的源端。第二个ILFD3 (ILFD32)使用尾晶体管放大注入信号,然后注入较低cct的源端。由于上部cct源端存在较强的二次谐波信号(2finj),因此在上部cct漏极端存在明显的锁定基波信号(finj)。ILFD31功耗低,为1.6 mW,锁定范围为3.4 GHz (92.5-95.9 GHz)。ILFD32功耗低至0.13 mW,锁定范围为18 GHz (91.8-109.8 GHz),是w波段CMOS ILFD3s中迄今为止报道的最佳结果之一。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
W-Band Divide-by-3 Injection-Locked Frequency Divider Using Stacked Cross-Coupled Transistors in 90 nm CMOS
We demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor (CCT) topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower CCTs and then inject the source terminals of the upper CCTs. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower CCTs. Due to the strong second harmonic signal (2finj) at the source terminals of the upper CCTs, there are notable locked fundamental signals (finj) at the drain terminals of the upper CCTs. ILFD31 consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s.
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