系统级建模和验证:一个全面的设计方法

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC Pub Date : 1994-02-28 DOI:10.1109/EDTC.1994.326811

P. Camurati, Fulvio Corno, P. Prinetto, C. Bayol, B. Soulas

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引用次数: 7

摘要

在系统级工作正引起越来越多的兴趣，因为它支持在进行硬件/软件分区之前探索几种备选方案。必须考虑到新的问题，例如所有步骤的确认和核实。本文提出了一种系统级设计方法，它支持系统级的描述、确认和验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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System-level modeling and verification: a comprehensive design methodology

Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level.<>

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Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

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