S. Summerfelt, T. Moise, K. Udayakumar, K. Boku, K. Remack, J. Rodriguez, J. Gertas, H. McAdams, S. Madan, J. Eliason, J. Groat, D. Kim, P. Staubs, M. Depner, R. Bailey
{"title":"低功耗130nm逻辑制程内的高密度8Mb 1T-1C铁电随机存取存储器","authors":"S. Summerfelt, T. Moise, K. Udayakumar, K. Boku, K. Remack, J. Rodriguez, J. Gertas, H. McAdams, S. Madan, J. Eliason, J. Groat, D. Kim, P. Staubs, M. Depner, R. Bailey","doi":"10.1109/ISAF.2007.4393151","DOIUrl":null,"url":null,"abstract":"Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.","PeriodicalId":321007,"journal":{"name":"2007 Sixteenth IEEE International Symposium on the Applications of Ferroelectrics","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process\",\"authors\":\"S. Summerfelt, T. Moise, K. Udayakumar, K. Boku, K. Remack, J. Rodriguez, J. Gertas, H. McAdams, S. Madan, J. Eliason, J. Groat, D. Kim, P. Staubs, M. Depner, R. Bailey\",\"doi\":\"10.1109/ISAF.2007.4393151\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.\",\"PeriodicalId\":321007,\"journal\":{\"name\":\"2007 Sixteenth IEEE International Symposium on the Applications of Ferroelectrics\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Sixteenth IEEE International Symposium on the Applications of Ferroelectrics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISAF.2007.4393151\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Sixteenth IEEE International Symposium on the Applications of Ferroelectrics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISAF.2007.4393151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process
Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.