{"title":"系统原型设计为一个16kbps自适应矢量量化波形编码器","authors":"J. Foster, S. Ardalan","doi":"10.1109/SSST.1990.138175","DOIUrl":null,"url":null,"abstract":"The system design of an adaptive vector quantizer (AVQ) for waveform coding is presented. The goal of this work is the development of a 16-kb/s AVQ coder prototype system which can be used as an alternative to 32-kb/s adaptive delta pulse code modulation (ADPCM). The major components of the board are an application-specific integrated-circuit (ASIC) AVQ chip, a 1 M*8 RAM, a 64-kb/s PCM codec, a 16-kb/s universal synchronous/asynchronous receiver/transmitter (USART), and clock circuitry. The system-level CAD tools are presented for an Apollo/Mentor graphics platform. The integration of ASIC chip design with system hardware/software description is discussed. Both chip- and board-level simulation, routing, library functionality, and fabrication turnaround are presented.<<ETX>>","PeriodicalId":201543,"journal":{"name":"[1990] Proceedings. The Twenty-Second Southeastern Symposium on System Theory","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"System prototype design for a 16-K bps adaptive vector quantization waveform coder\",\"authors\":\"J. Foster, S. Ardalan\",\"doi\":\"10.1109/SSST.1990.138175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The system design of an adaptive vector quantizer (AVQ) for waveform coding is presented. The goal of this work is the development of a 16-kb/s AVQ coder prototype system which can be used as an alternative to 32-kb/s adaptive delta pulse code modulation (ADPCM). The major components of the board are an application-specific integrated-circuit (ASIC) AVQ chip, a 1 M*8 RAM, a 64-kb/s PCM codec, a 16-kb/s universal synchronous/asynchronous receiver/transmitter (USART), and clock circuitry. The system-level CAD tools are presented for an Apollo/Mentor graphics platform. The integration of ASIC chip design with system hardware/software description is discussed. Both chip- and board-level simulation, routing, library functionality, and fabrication turnaround are presented.<<ETX>>\",\"PeriodicalId\":201543,\"journal\":{\"name\":\"[1990] Proceedings. The Twenty-Second Southeastern Symposium on System Theory\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-03-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990] Proceedings. The Twenty-Second Southeastern Symposium on System Theory\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SSST.1990.138175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990] Proceedings. The Twenty-Second Southeastern Symposium on System Theory","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSST.1990.138175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
System prototype design for a 16-K bps adaptive vector quantization waveform coder
The system design of an adaptive vector quantizer (AVQ) for waveform coding is presented. The goal of this work is the development of a 16-kb/s AVQ coder prototype system which can be used as an alternative to 32-kb/s adaptive delta pulse code modulation (ADPCM). The major components of the board are an application-specific integrated-circuit (ASIC) AVQ chip, a 1 M*8 RAM, a 64-kb/s PCM codec, a 16-kb/s universal synchronous/asynchronous receiver/transmitter (USART), and clock circuitry. The system-level CAD tools are presented for an Apollo/Mentor graphics platform. The integration of ASIC chip design with system hardware/software description is discussed. Both chip- and board-level simulation, routing, library functionality, and fabrication turnaround are presented.<>
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