High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier

In the field of VLSI, enhancement is prominent. Arithmetic circuits are one of the influential sectors in today’s end products of electronics, where multipliers are one of the deciding factors of efficiency. Multiplier plays an important role in different applications such as digital signal processing in which it acts as a key hardware block. As time rolls down, the technology exposed the ways for the initiation of many hardware and software implementations of the faster multipliers. One among them is the Montgomery multiplier. The fundamental operation in the Montgomery multiplier is the modular multiplication. It is mainly used in FIR filters, which in-turn has numerous applications such as speech analysis, multi-rate signal processing, adaptive filters, and averaging filters. With the usage of proposed compressor in the conventional design of the multiplier, the number of transistor count has been declined by a significant amount and made the design into an optimal area design. This paper presents a modified Montgomery multiplier design and its implementation in the 5th order FIR filter. The entire design simulation is carried out using CMOS and PTL logic in 45 nm technology. There is an escalation in the result outcomes, and the multiplier has an area efficiency of 65% and a power reduction of about 68% in comparison with conventional design.