FPGA based image de-hazing architecture for real time applications

This paper proposes the design and Field Programmable Gate Array (FPGA) architecture of dark channel prior algorithm for image de-hazing. The RGB hazed image is read in the form of 3×3 patches (9 Pixels) and minimum intensity pixels are obtained from each patch. These minimum intensity pixels form a dark vector. Atmospheric light for each color is estimated using this dark vector. Transmission map is computed by atmospheric light. Guided filter is used to refine the transmission map and finally de-hazed image is recovered. The proposed architecture comprises of 6 cores and is implemented usingVerilog HDL and Xilinx ISE Design Suite 14.5. The proposed image de-hazing architecture is validated by comparing the simulation results with MATLAB results. The proposed architecture is synthesized for Xilinx Zynq board, Device XC7Z045, Package FFG900, Speed −3. Synthesis results show that proposed design consumes 24568 Slice registers and 18644 LUTs. Furthermore, the design consumes 71 BRAMs and can operate on Maximum Frequency of142.786MHzwith minimum clock period of 7.003ns.