R. Singanamalla, C. Ravit, G. Vellianitis, J. Pétry, V. Paraschiv, J. van Zijl, S. Brus, M. Verheijen, R. Weemaes, M. Kaiser, J. van Berkum, P. Bancken, R. Vos, H. Yu, K. De Meyer, S. Kubicek, S. Biesemans, J. Hooker
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引用次数: 1
摘要
我们使用标准的高温栅第一金属插入多晶硅(MIPS)工艺流程报道了HfSiON栅极电介质上MoOxNy的带边pet阈值电压(Vt ~ 0.28 V)。我们还报道了使用MoO x/SiON栅极堆栈的p- fet Vt为0.45 V，满足45nm高Vt CMOS技术的要求。通过使用MoOx/SiON和MoOx/HfSiON栅极堆栈，与我们的基线多晶硅/SiON相比，性能提高了30%。与我们的基线poly/SiON器件相比，具有MoOxNy门控堆栈的器件也显示出优异的介质完整性，例如器件迁移率，NBTI和TDDB特性
Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET Devices
We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoOxNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices
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