C. Torres-Huitzil, S. Maya-Rueda, M. Arias-Estrada
{"title":"用于实时应用的可重构视觉系统","authors":"C. Torres-Huitzil, S. Maya-Rueda, M. Arias-Estrada","doi":"10.1109/FPT.2002.1188693","DOIUrl":null,"url":null,"abstract":"Recently, a growing community of researchers has used reconfigurable hardware systems to solve computationally intensive problems. Reconfigurability provides optimised processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for real-time computer vision applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture. Some preliminary results are presented and discussed.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A reconfigurable vision system for real-time applications\",\"authors\":\"C. Torres-Huitzil, S. Maya-Rueda, M. Arias-Estrada\",\"doi\":\"10.1109/FPT.2002.1188693\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently, a growing community of researchers has used reconfigurable hardware systems to solve computationally intensive problems. Reconfigurability provides optimised processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for real-time computer vision applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture. Some preliminary results are presented and discussed.\",\"PeriodicalId\":355740,\"journal\":{\"name\":\"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPT.2002.1188693\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPT.2002.1188693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A reconfigurable vision system for real-time applications
Recently, a growing community of researchers has used reconfigurable hardware systems to solve computationally intensive problems. Reconfigurability provides optimised processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for real-time computer vision applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture. Some preliminary results are presented and discussed.