Algorithmic Compiler based FPGA Implementation of Iterative Time-Domain Algorithm for Sparse Channel Estimation

In this paper, we present an algorithmic compiler based field-programmable gate array (FPGA) implementation of iterative time domain sparse channel estimation algorithm for IEEE 802.22 standard. The algorithm is implemented on Xilinx Kintex-7 410T FPGA in the National Instrument’s (NI) Universal Software Radio Peripheral 2952R operating at 20 MHz by using high throughput math functions. The algorithmic compiler in the NI LabVIEW Communication System Design Suite converts the high-level description of entire algorithm to very high speed integrated circuit hardware description language. Actual usage of FPGA’s resource such as slices, lookup tables and others are also provided. Additionally, we compare the bit error rate performance of the considered algorithm for different modulation techniques obtained from MATLAB and FPGA implementations.