Design of Hardware Accelerators to Compute Parametric Capacitance Tables

Advances in VLSI process have created a significant computational burden on process calibration, and the generation of capacitance tables of pre-characterized 2D cross-section layout from physical parameters such as dielectrics and layer thickness. In this paper we describe a high-level synthesis approach to design hardware accelerators to alleviate this concern. Design of a hardware accelerator which can produce capacitance tables for multiple layer and corner combinations is presented. An innovative approach (lambda compression) to reduce the volume of output is also described. Simulation shows that our pipelined superscalar approach can generate and solve a capacitance problem in amortized 4us at 500MHz clock, which is three orders of magnitude faster than state-of-art software based solutions. Interestingly, the optimizations suggested by an hardware implementation also give very good results on a CPU implementation, and this is yet another approach to software optimization.