Design and Implementation of Tunable Network on Chip for FPGA applications

Conventionally buses or crossbar interconnects were used as interconnects for FPGA or ASIC. With the passage of time and growth of technology Network on chip (NoC) was developed. NoC proved to be an efficient and effective alternative for an interconnecting problem in large System-on-Chip (SoCs). This paper aims to develop a tunable NoC for FPGA which utilizes the maximum potential of FPGA resources so that more resources could be incorporated in the available space thereby making it suitable for multipurpose SoC platform. Also, it could be adapted to any kind of FPGA device and multi-code devices. This tunable NoC requires fewer resources and supports higher clock frequency. It also can provide a better average latency.