Increasing Autonomy of I/O Cores in Heterogeneous FPGA-SoCs for Data Acquisition Applications

As the architectures of FPGA-SoCs become more complex, it is increasingly important to find new ways to optimize the utilization of the interconnects that connect the various components like I/O cores, processors, and memories. Here we present a semi-autonomous soft I2C core and a systematic analysis of the performance characteristics of this core in a Linux system. Compared to a conventional I2C core, the devised core used with a new API reduces the average irq processor utilization in monitoring applications by 87.28% for SMBus Read Word operations and by 81.59% for SMBus Write Word operations, while maximizing I2C bus throughput and improving temporal predictability of I2C message transfers. The results show that overhead of interrupt processing to periodically fill a TX FIFO can be substantial and that designing an I/O core to be less dependent on a general-purpose processor can improve system performance considerably.