SHA-3-LPHP: Hardware Acceleration of SHA-3 for Low-Power High-Performance Systems

In the last decade, the world transitioned from using Secure Hash Algorithm 1 (SHA-1) to Secure Hash Algorithm 2 (SHA-2) due to the flaws in SHA-1. However, SHA-2 still uses a similar internal structure with the same mathematical flaws as its predecessor. Safety in SHA-2 is attributed to the increased length of its output compared to SHA-1. Since then, a new hashing algorithm, SHA-3 has been introduced, which does not share the same flaws as its other family members. However, the transition to SHA-3 has not been complete due to lack of software and hardware support for SHA-3 as well as performance issues. The performance limitation, however, is only present in software implementations. In this paper, we propose a new implementation of SHA-3 based on FPGA hardware (SHA-3-LPHP), to be integrated in the architecture of low-power devices. SHA-3-LPHP achieves three orders magnitude improvement in execution time as compared to full software implementations, furthermore, requiring less energy, hence making it an excellent candidate for low-power and high-performance systems.