Variable fractional rate digital down converter for satellite communication

This paper demonstrates an innovative variable fractional rate Digital Down Converter(DDC) architecture for satellite communication where the carrier frequency and output sample rate can be changed dynamically at run time. The proposed algorithm is highly modular and generic so that the DDC can decimate by any fractional ratio i.e. the ADC sampling rate may be any integer or non-integer multiple of output sample rate from DDC. The algorithm is verified by evaluating the bit error rate(BER) performance of Binary Phase Shift Keying(BPSK) modulation with theoretical BER in the presence of additive white Gaussian noise (AWGN) in Matlab. Xilinx FPGA (Kintex-7) realizes the novel DDC hardware along with the demodulator implemented in DSP processor which performs timing synchronization, frequency offset estimation and correction. Though the primary use of the design is in satellite communication, the same applies to other multi-standard radio based communication like GSM, CDMA, WCDMA, WiMAX, LTE.