高级综合的超过程概念及其VHDL建模

P. Keresztes, I. Agotai
{"title":"高级综合的超过程概念及其VHDL建模","authors":"P. Keresztes, I. Agotai","doi":"10.1109/EURDAC.1993.410680","DOIUrl":null,"url":null,"abstract":"The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"The concept of superprocesses for high-level synthesis and their VHDL modelling\",\"authors\":\"P. Keresztes, I. Agotai\",\"doi\":\"10.1109/EURDAC.1993.410680\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410680\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410680","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

作者将具有并发控制流的进程描述为超进程。提出了一种结合VHDL和数据/控制流图描述的方法,以创建包含并发控制流的抽象级行为规范。揭示了仿真编译器的功能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The concept of superprocesses for high-level synthesis and their VHDL modelling
The authors describe a process with a concurrent control flow as a superprocess. A combined VHDL and data/control flow graph description is proposed so as to create abstract level behavioral specifications containing a concurrent control flow. The functions of the simulation compiler are exposed.<>
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