多值密码处理器的防篡改寄存器设计

Yuichi Baba, N. Homma, A. Miyamoto, T. Aoki
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引用次数: 2

摘要

提出了一种用于多值密码处理器的防篡改寄存器设计。提出了电压模式和电流模式寄存器来隐藏功耗和输入数据之间的依赖关系。为此,电压模式寄存器以互补的方式激活两个触发器中的任何一个,而电流模式寄存器保持与输入值无关的电流信号的数量。本文还将这两个寄存器应用于多值电流模式逻辑中的RSA处理器,并采用90nm工艺技术通过HSIM仿真评估了其功率特性。结果表明,与传统设计相比,所提出的设计能够以较低的开销实现恒定的功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors
This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.
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