State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis

The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo.cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are common starting points for various sequential synthesis and verification tools.<>