Mathematical Models Applied to On-Chip Network on FPGA for Resource Estimation

One main challenge of prototyping a SoC (System on Chip) on FPGA (Field Programmable Gate Array) is to tune at best the communication architecture according to the task graph of an application and the available resources of the chosen FPGA. The exploration of the potential design candidates is time consuming, tedious and does not scale. The sheer number of parameters leads to a wide design space that cannot be explored in a limited time. The aim of this paper is to identify mathematical models applied to NoC to estimate FPGA resources. Mathematical models are obtained from a database containing a set of observed results. Using the database, the Pearson's correlation coefficient and the variable clustering are used to set the most appropriate variables and constants. The mathematical models are obtained and then validated with a set of experimental results. The validation shows that the error rate between observed results and the analytically estimated results is less than 5%. The designer can therefore tune the NoC in shorter exploration time.