HEVC解码器中有效SAO的硬件设计

Seungyong Park, K. Ryoo
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引用次数: 15

摘要

本文提出了一种处理时间短、计算量少、硬件面积小的高性能HEVC解码器SAO硬件架构。提出的SAO硬件架构引入了设计处理8×8 CU以减少硬件面积,并使用内部寄存器支持64×64 CU处理。与以前自上而下的块分区不同,它使用自下而上的块分区来最小化计算量和处理时间。将所提出的架构与台积电180nm库综合后,栅极面积为30.7k,最大频率为250MHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The hardware design of effective SAO for HEVC decoder
In this paper, we propose an SAO hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC decoder. The proposed SAO hardware architecture introduces the design processing 8×8 CU to reduce the hardware area and uses internal registers to support 64×64 CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC 180nm library, the gate area is 30.7k and the maximum frequency is 250MHz.
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