{"title":"HEVC解码器中有效SAO的硬件设计","authors":"Seungyong Park, K. Ryoo","doi":"10.1109/GCCE.2013.6664837","DOIUrl":null,"url":null,"abstract":"In this paper, we propose an SAO hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC decoder. The proposed SAO hardware architecture introduces the design processing 8×8 CU to reduce the hardware area and uses internal registers to support 64×64 CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC 180nm library, the gate area is 30.7k and the maximum frequency is 250MHz.","PeriodicalId":294532,"journal":{"name":"2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"The hardware design of effective SAO for HEVC decoder\",\"authors\":\"Seungyong Park, K. Ryoo\",\"doi\":\"10.1109/GCCE.2013.6664837\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose an SAO hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC decoder. The proposed SAO hardware architecture introduces the design processing 8×8 CU to reduce the hardware area and uses internal registers to support 64×64 CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC 180nm library, the gate area is 30.7k and the maximum frequency is 250MHz.\",\"PeriodicalId\":294532,\"journal\":{\"name\":\"2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GCCE.2013.6664837\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCCE.2013.6664837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The hardware design of effective SAO for HEVC decoder
In this paper, we propose an SAO hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC decoder. The proposed SAO hardware architecture introduces the design processing 8×8 CU to reduce the hardware area and uses internal registers to support 64×64 CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC 180nm library, the gate area is 30.7k and the maximum frequency is 250MHz.