用于评估设计的可测试性的简化度量

L. Ungar, S. Davidson
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引用次数: 6

摘要

可测试性设计(DFT)评估是一个非常复杂且依赖于电路的问题。为了简化分析并将方法更广泛地应用于不同的电路类型和不同级别的组装,我们将重点放在识别可测试性差的区域上。我们引入了我们称为Sensitized Path Oriented teststability Scoring™或SPOTS™的指标,在需要检测和诊断故障模式的所有点执行,以发现不良的可测试性。一旦在设计阶段早期识别出问题,特别是当它与电路节点和故障模式相关时,通过DFT纠正问题所需的补救措施可能非常实用。spot测量四个可测试性属性——可控性、可区分性、测试资源成本,以及由于缺乏可测试性而导致的测试逃逸。该指标通过利用敏化路径来测量电路可控性,简化了以前的可测试性技术。敏化路径的使用大大减少了所需的分析,虽然它可能无法提供可测试性验证,但它成功地突出了缺乏可测试性的区域。可控性度量(CM)提供了一个数字,对应于敏化路径所需的步骤数。可分辨度度量(DM)衡量将一个故障从其他故障中隔离出来的难度。测试资源成本(RC),包括测试程序集(TPS)开发成本和测试设备需求,并以货币货币表示。惩罚成本(PC)以货币形式度量因逃避测试中检测而未测试的节点所产生的成本。将这些指标与每个节点上的故障模式关联起来,可以创建一个表,显示存在可测试性问题的地方。设计人员和可测试性分析人员可以通过改变故障检测和隔离要求、改进测试资源和/或重新设计被测单元(UUT)来共同解决这些问题。这种形式的分析更容易使用,适用于任何级别的组装-集成电路,电路板或系统。它甚至可以被那些采购商业现货(COTS)产品的人用来比较竞争产品的支持成本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Simplified metrics for evaluating designs for testability
Design for Testability (DFT) evaluation is quite complex and circuit dependent. To simplify the analysis and to apply the methodology more generally to different circuit types and different levels of assembly, we focus our efforts on identifying areas of poor testability. We introduce metrics we call Sensitized Path Oriented Testability Scoring ™ or SPOTS ™, performed at all points where failure modes are to be detected and diagnosed, to spot poor testability. Once the problem is identified early in the design stage, especially when it is correlated with a circuit node and a failure mode, the remedy needed to correct the problem through DFT can be quite practical. SPOTS measures four testability attributes - controllability, distinguishability, test resource costs, and test escapes due to lack of testability. The metrics simplify previous testability techniques, by utilizing sensitized paths to measure circuit controllability. The use of sensitized paths greatly reduces the analysis required, and while it may not offer validation of testability, it succeeds in highlighting areas that lack testability. Controllability metric (CM) provides a number corresponding to the number of steps required to sensitize a path. Distinguishability metric (DM) measures the difficulty of isolating one fault from others. Test resource cost (RC), includes test program set (TPS) development costs and test equipment requirements, and is expressed in monetary currency. Penalty cost (PC) measures in currency the cost incurred for nodes left untested by escaping detection in tests. Associating each of these metrics to failure modes at each node creates a table that reveals where testability problems exist. Designers and testability analysts can work together to resolve them either by altering the fault detection and isolation requirements, improving test resources and/or redesigning the unit under test (UUT). This form of analysis is simpler to use and is applicable to any level of assembly — IC, board or system. It can even be utilized by those procuring commercial off the shelf (COTS) products to compare support costs for competing products.
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