5 GHz /spl Sigma//spl Delta/模数转换器，带极性交替反馈比较器

GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997 Pub Date : 1997-10-12 DOI:10.1109/GAAS.1997.628245

T. Miyashita, A. Olmos, M. Nihei, Y. Watanabe

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引用次数: 1

摘要

采用0.4-/spl mu/m InGaP/- ingaas增强和耗尽模式高电子迁移率晶体管(E/D HEMT)技术，设计并制作了一个5 GHz过采样、100 MHz带宽的连续时间二阶/spl Sigma//spl Delta/模数转换器(ADC)。我们提出了极性交替反馈(PAF)技术来提高采样频率，并将其应用于ADC电路的设计中。该ADC在4.9 GHz差分时钟下的信噪比(SNR)为43 dB (7.3 bits)，功耗为400 mW。

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5 GHz /spl Sigma//spl Delta/ analog-to-digital converter with polarity alternating feedback comparator

We designed and fabricated a 5 GHz oversampling, 100 MHz bandwidth continuous time second order /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using 0.4-/spl mu/m InGaP/-InGaAs enhancement and depletion mode high electron mobility transistor (E/D HEMT) technology. We propose the polarity alternating feedback (PAF) technique for enhancing the sampling frequency and have applied it in the design of an ADC circuit. The fabricated ADC shows a signal-to-noise ratio (SNR) of 43 dB (7.3 bits) under a differential clock of 4.9 GHz with a power dissipation of 400 mW.

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GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997

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