J. Okuno, T. Yonai, Takafumi Kunihiro, Kenta Konishi, M. Materano, T. Ali, M. Lederer, K. Seidel, T. Mikolajick, U. Schroeder, M. Tsukamoto, T. Umebayashi
{"title":"hf0.5 zr0.5 o2基1T1C FeRAM存储阵列疲劳与恢复现象的论证","authors":"J. Okuno, T. Yonai, Takafumi Kunihiro, Kenta Konishi, M. Materano, T. Ali, M. Lederer, K. Seidel, T. Mikolajick, U. Schroeder, M. Tsukamoto, T. Umebayashi","doi":"10.1109/EDTM53872.2022.9797943","DOIUrl":null,"url":null,"abstract":"Recently, a novel, one-transistor one-capacitor (1T1C) type, ferroelectric random-access memory (FeRAM) array was developed, and its operation was experimentally demonstrated. This array was based on ferroelectric Hf0.5Zr0.5O2 (HZO), with a capacitor under bitline structure, and was compatible with system-on-chip. In this work, bitline voltage difference distributions were examined via cycling tests and observed to not deteriorate during fatigue and recovery stress, indicating uniform charge trapping and domain de-pinning within the ferroelectric domains in the test chip.","PeriodicalId":158478,"journal":{"name":"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Demonstration of Fatigue and Recovery Phenomena in Hf0.5Zr0.5O2-based 1T1C FeRAM Memory Arrays\",\"authors\":\"J. Okuno, T. Yonai, Takafumi Kunihiro, Kenta Konishi, M. Materano, T. Ali, M. Lederer, K. Seidel, T. Mikolajick, U. Schroeder, M. Tsukamoto, T. Umebayashi\",\"doi\":\"10.1109/EDTM53872.2022.9797943\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently, a novel, one-transistor one-capacitor (1T1C) type, ferroelectric random-access memory (FeRAM) array was developed, and its operation was experimentally demonstrated. This array was based on ferroelectric Hf0.5Zr0.5O2 (HZO), with a capacitor under bitline structure, and was compatible with system-on-chip. In this work, bitline voltage difference distributions were examined via cycling tests and observed to not deteriorate during fatigue and recovery stress, indicating uniform charge trapping and domain de-pinning within the ferroelectric domains in the test chip.\",\"PeriodicalId\":158478,\"journal\":{\"name\":\"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)\",\"volume\":\"146 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTM53872.2022.9797943\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTM53872.2022.9797943","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Demonstration of Fatigue and Recovery Phenomena in Hf0.5Zr0.5O2-based 1T1C FeRAM Memory Arrays
Recently, a novel, one-transistor one-capacitor (1T1C) type, ferroelectric random-access memory (FeRAM) array was developed, and its operation was experimentally demonstrated. This array was based on ferroelectric Hf0.5Zr0.5O2 (HZO), with a capacitor under bitline structure, and was compatible with system-on-chip. In this work, bitline voltage difference distributions were examined via cycling tests and observed to not deteriorate during fatigue and recovery stress, indicating uniform charge trapping and domain de-pinning within the ferroelectric domains in the test chip.