栅极长度缩放对UTBOX FDSOI器件的影响:无扩展结构的数字/模拟性能

T. Nicoletti, S. Santos, L. Almeida, J. Martino, M. Aoulaiche, A. Veloso, M. Jurczak, E. Simoen, C. Claeys
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引用次数: 14

摘要

在本文中,我们从直流测量中探讨了不同温度下栅极长度标度对超薄埋藏氧化物(UTBOX)完全耗尽绝缘体上硅(FDSOI)器件主要数字/模拟参数的影响。将标准结参考器件与无延伸参考器件进行比较,后者除了具有更高的离子/离合比(Ion/Ioff ratio)、VEA和AV外,还具有更小的器件长度,如改进的DIBL、SS和IGIDL。温度倾向于降低所有器件参数,尽管无延伸结构显示出不太容易受到其影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The impact of gate length scaling on UTBOX FDSOI devices: The digital/analog performance of extension-less structures
In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved DIBL, SS and IGIDL apart from the higher Ion/Ioff ratio, VEA and AV. The temperature tends to degrade all the device parameters although the extension-less structures show to be less susceptible to its influence.
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