{"title":"一种用于实时立体视觉处理器的单芯片VLSI架构","authors":"F. Jutand, S. Maginot, N. Demassieux, H. Maître","doi":"10.1109/ICASSP.1988.197009","DOIUrl":null,"url":null,"abstract":"The architecture of a single-chip stereo vision processor is presented. It can carry out in real time a dynamic programming algorithm (or a Viterbi algorithm) to compute for each pixel the distance between two corresponding lines. An on-chip surviving-paths memorization and decoding is also described. A rough evaluation for a 1.2- mu m CMOS process provides an area of less than 70 mm/sup 2/.<<ETX>>","PeriodicalId":448544,"journal":{"name":"ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A single chip VLSI architecture for a real time stereo vision processor\",\"authors\":\"F. Jutand, S. Maginot, N. Demassieux, H. Maître\",\"doi\":\"10.1109/ICASSP.1988.197009\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture of a single-chip stereo vision processor is presented. It can carry out in real time a dynamic programming algorithm (or a Viterbi algorithm) to compute for each pixel the distance between two corresponding lines. An on-chip surviving-paths memorization and decoding is also described. A rough evaluation for a 1.2- mu m CMOS process provides an area of less than 70 mm/sup 2/.<<ETX>>\",\"PeriodicalId\":448544,\"journal\":{\"name\":\"ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing\",\"volume\":\"78 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-04-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASSP.1988.197009\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASSP.1988.197009","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
介绍了一种单片立体视觉处理器的结构。它可以实时执行动态规划算法(或Viterbi算法),计算每个像素对应的两条线之间的距离。还描述了一种片上生存路径记忆和解码方法。粗略评估1.2 μ m CMOS工艺提供的面积小于70 mm/sup /。
A single chip VLSI architecture for a real time stereo vision processor
The architecture of a single-chip stereo vision processor is presented. It can carry out in real time a dynamic programming algorithm (or a Viterbi algorithm) to compute for each pixel the distance between two corresponding lines. An on-chip surviving-paths memorization and decoding is also described. A rough evaluation for a 1.2- mu m CMOS process provides an area of less than 70 mm/sup 2/.<>