Efficient scalable hardware architecture for highly performant encoded neural networks

Different neural network models have been proposed to design efficient associative memories like Hopfield networks, Boltzmann machines or Cogent confabulation. Compared to the classical models, Encoded Neural Network (ENN) is a recently introduced formalism with a proven higher efficiency. This model has been improved through different contributions like Clone-based ENN (CbNNs) or Sparse ENNs (S-ENNs) which enhance either the capacity of the original ENN or its retrieving performances. However, only very few works explored its hardware implementation for embedded applications. In this paper, we introduce a clone-based sparse neural network model (SC-ENN), that gathers the enhancements of the existing approaches in a single formal model. In addition, we present a dedicated scalable hardware architecture to implement SC-ENN. This work leads to significant complexity and area reduction without affecting neither memorizing nor retrieving performances. By only handling the most relevant information provided by the model, our proposed approach is far less expensive compared to state of the art solutions.