Optimized Arithmetic and Logical Unit Design using Reversible Logic Gates

The modern world, Digital electronics systems are compact and faster. But, the major problem of these systems are power dissipation. The Power dissipation have different variants such as a static power, dynamic power, short circuit and leakage current dissipation. In VLSI Design, the power consumption plays an important role. In order to minimize the power dissipation there are many different low power methodologies are used such as a multi-Vth method, clock gating and reversible logic gate method. The major advantages of a circuit designing using a reversible logic gates will be compatible with an obtainable resources and the reversible Gates have a zero heat dissipation. The Arithmetic and Logical Unit is fundamental part of a computing systems. This paper, presents a Design of low garbage Reversible Arithmetic and logical unit design for computing system and the design includes Adder, subtractor and Multiplier blocks. The functionality of a design performance, trash outputs, Quantum cost are analysed. The proposed design has a 11 trash outputs and 57 quantum costs. The design is coded on Verilog HDL and synthesized, simulated by a Xilinx software.