差分DIMM OpenCAPI内存接口高速通道鲁棒性与可扩展性研究

Biao Cai, Kevin Mcilvain, Junyan Tang, Kyle Giesen, Zhaoqing Chen, Hongqing Zhang, B. Beaman, Chris Steffen, Zhineng Fan, Victor Mahran, Luis Fukazawa, Roc Lv
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引用次数: 0

摘要

JEDEC正在定义差分DIMM (DDIMM),它使用OMI作为主机接口,目前的数据传输率为25.6Gb/s,未来的数据传输率为51.2Gb/s。2019 ~ 2020年之前的一项研究[13]对初始DDR4 DDIMM工程样品进行了全通道模拟和电气测试,证明了在25.6Gb/s OMI总线数据速率下实现BER 10^-15的可行性。在本研究中,我们将对25.6Gb/s OMI通道鲁棒性在生产环境下使用更大DDR4 DDIMM样本量的测试结果进行分析。此外,本研究将探索OMI总线数据速率规模为32Gb/s的全通道时域眼图分析,误码率为10^-15。2018 ~ 20年的先前研究[1],[13]得出结论,工业标准U/R/LR DIMM中使用的典型覆铜层压板(CCL)和预浸料材料相对于更好的参考材料在25.6Gb/s OMI总线数据速率下导致信号完整性下降,而采用混合层压板材料的改进DDIMM PCB堆叠显示出足够的空间。本研究的DDIMM PCB堆叠包括这种混合材料作为基准和低损耗的Megtron 6材料集。DDIMM将与存储网络行业协会(SNIA) SFF-TA-1002高速连接器配对。SFF-TA-1002连接器的DDIMM PCB接触接口的信号完整性挑战已在2018 ~ 20年的先前研究中得到强调[1],[13]。本研究将讨论接触界面的鲁棒性。综上所述,本文将介绍DDR4 DDIMM 25.6Gb/s OMI通道鲁棒性研究和计划在产品发布时用于DDR5 DDIMM的32Gb/s OMI通道可扩展性研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Differential DIMM OpenCAPI Memory Interface High Speed Channel Robustness and Scalability Study
Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate being specified at 25.6Gb/s at present and at 51.2Gb/s in the future. A prior 2019∼20 study [13] of full channel simulation and electrical test with initial DDR4 DDIMM engineering samples demonstrated the feasibility to achieve BER 10^-15 at 25.6Gb/s OMI bus data rate. In this study, the test result in production environment with much larger DDR4 DDIMM sample size will be analyzed for 25.6Gb/s OMI channel robustness. In addition, this study will explore the OMI bus data rate scale to 32Gb/s with the full channel time domain eye diagram analysis with BER at 10^-15. The prior studies in 2018∼20 [1], [13] concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard U/R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate while the improved DDIMM PCB stack-up with hybrid laminate material set has shown adequate margin. The DDIMM PCB stack-ups of this study include this hybrid material as baseline and lower loss Megtron 6 like material sets. DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector. The signal integrity challenges of DDIMM PCB contact interface to SFF-TA-1002 connector have been highlighted in the prior studies in 2018∼20[1], [13]. This study will discuss the contact interface robustness. In summary, this paper will present DDR4 DDIMM 25.6Gb/s OMI channel robustness study and the OMI channel scalability study to 32Gb/s which is planned for DDR5 DDIMM at product launch.
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