{"title":"一个8位,8-GS/s等效采样时域模数转换器","authors":"Yu Zhu, Maliang Liu, Zhangming Zhu","doi":"10.1109/EDSSC.2019.8754327","DOIUrl":null,"url":null,"abstract":"The paper proposes an 8-bit, 8-GS/s time domain analog-to-digital converter (TD-ADC) with equivalent time sampling technology. The prototype was fabricated in 65 nm CMOS technology. This ADC has a high area efficiency. The core area of the chip is only $320 \\mu {\\mathrm{m} \\times 300\\mathrm{m}}$. The measured SFDR and SNDR are over 43.0 dB and 57.6 dB with a Nyquist input.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An 8-bit, 8-GS/s Equivalent Sampling Time Domain Analog-to-digital Converter\",\"authors\":\"Yu Zhu, Maliang Liu, Zhangming Zhu\",\"doi\":\"10.1109/EDSSC.2019.8754327\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper proposes an 8-bit, 8-GS/s time domain analog-to-digital converter (TD-ADC) with equivalent time sampling technology. The prototype was fabricated in 65 nm CMOS technology. This ADC has a high area efficiency. The core area of the chip is only $320 \\\\mu {\\\\mathrm{m} \\\\times 300\\\\mathrm{m}}$. The measured SFDR and SNDR are over 43.0 dB and 57.6 dB with a Nyquist input.\",\"PeriodicalId\":183887,\"journal\":{\"name\":\"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2019.8754327\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2019.8754327","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8-bit, 8-GS/s Equivalent Sampling Time Domain Analog-to-digital Converter
The paper proposes an 8-bit, 8-GS/s time domain analog-to-digital converter (TD-ADC) with equivalent time sampling technology. The prototype was fabricated in 65 nm CMOS technology. This ADC has a high area efficiency. The core area of the chip is only $320 \mu {\mathrm{m} \times 300\mathrm{m}}$. The measured SFDR and SNDR are over 43.0 dB and 57.6 dB with a Nyquist input.