Low cost VLSI discrete wavelet transform and FIR filters architectures for very high-speed signal and image processing

This paper presents new VLSI architectures for finite impulse response (FIR) filters and discrete wavelet transform, intended for very high-speed signal and image processing. The proposed architectures, based on combining pipeline and parallel arithmetic methods, provide a new and very fast convolution approach with a reduced critical path. The key to this is a clever use of D-latches and multipliers which are efficiently distributed. Furthermore, an advanced discrete wavelet transform (DWT) approach, with an area-efficient architecture, is designed to produce one output in every clock cycle. As a result, a very high-speed is attained. The proposed structure can increase the work frequency (85%) at a low cost of additional hardware elements (55%). The systems are verified, using JPEG2000 coefficients filters, on Xilinx Field Programmable Gate Array (FPGA) devices.