{"title":"低成本环境下SoC低功耗多链编码方案","authors":"Po-Han Wu, J. Rau","doi":"10.1109/TEST.2009.5355633","DOIUrl":null,"url":null,"abstract":"In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels (which is less than [1]) and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing [1] and our method. The average of improvement/ hardware is 16%/6%.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low power multi-chains encoding scheme for SoC in low-cost environment\",\"authors\":\"Po-Han Wu, J. Rau\",\"doi\":\"10.1109/TEST.2009.5355633\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels (which is less than [1]) and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing [1] and our method. The average of improvement/ hardware is 16%/6%.\",\"PeriodicalId\":419063,\"journal\":{\"name\":\"2009 International Test Conference\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2009.5355633\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2009.5355633","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power multi-chains encoding scheme for SoC in low-cost environment
In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels (which is less than [1]) and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing [1] and our method. The average of improvement/ hardware is 16%/6%.
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