图形码迭代解码器的设计与FPGA实现

Bharathram Sivasubramanian, W. Gross, H. Leib
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引用次数: 0

摘要

这项工作提出了一个现场可编程门阵列(FPGA)实现最小和迭代解码算法的(8,4)扩展汉明码使用可重构计算系统。Mitrion-C高级语言(HLL)用于fpga编程,因为它为基于fpga的原型设计和硬件设计的功能验证提供了灵活的工具。本文还提出了最小和解码器中最小步进的硬件高效实现,该实现消除了浮点乘法器的使用。最小和算法提供的并行性在硬件中被利用,导致比优化的软件实现提高15倍的速度。硬件实现的性能与计算机模拟预测的性能基本一致,验证了硬件设计的正确性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design and FPGA implementation of iterative decoders for codes on graphs
This work presents a Field Programmable Gate Array (FPGA) implementation of the Min-Sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the Min-step in the Min-Sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the Min-Sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.
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