{"title":"图形码迭代解码器的设计与FPGA实现","authors":"Bharathram Sivasubramanian, W. Gross, H. Leib","doi":"10.1109/CCECE.2009.5090295","DOIUrl":null,"url":null,"abstract":"This work presents a Field Programmable Gate Array (FPGA) implementation of the Min-Sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the Min-step in the Min-Sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the Min-Sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.","PeriodicalId":153464,"journal":{"name":"2009 Canadian Conference on Electrical and Computer Engineering","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and FPGA implementation of iterative decoders for codes on graphs\",\"authors\":\"Bharathram Sivasubramanian, W. Gross, H. Leib\",\"doi\":\"10.1109/CCECE.2009.5090295\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a Field Programmable Gate Array (FPGA) implementation of the Min-Sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the Min-step in the Min-Sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the Min-Sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.\",\"PeriodicalId\":153464,\"journal\":{\"name\":\"2009 Canadian Conference on Electrical and Computer Engineering\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Canadian Conference on Electrical and Computer Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.2009.5090295\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Canadian Conference on Electrical and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.2009.5090295","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and FPGA implementation of iterative decoders for codes on graphs
This work presents a Field Programmable Gate Array (FPGA) implementation of the Min-Sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the Min-step in the Min-Sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the Min-Sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.