90纳米及以上的器件特性及其对电路设计的影响

IEEE International Electron Devices Meeting 2003 Pub Date : 2003-12-08 DOI:10.1109/IEDM.2003.1269162

C. H. Diaz, K. Fung, S.M. Cheng, K. Cheng, S.W. Wang, H. Huang, Y. Leung, M. Tsai, C.C. Wu, C.C. Lin, Mi-Chang Chang, D. Tang

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引用次数: 5

摘要

为了协调缩放驱动的基本材料限制与行业发展需求，需要灵活的CMOS技术以及工艺开发和电路/系统设计之间更紧密的交互，以有效地实现片上系统(SoC)。本文讨论了与电源缩放、性能泄漏功率优化、栅极介电缩放、应变si增强和I/O支持相关的问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Device properties in 90 nm and beyond and implications on circuit design

To reconcile scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization, gate dielectric scaling, strain-Si enhancement and I/O support.

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IEEE International Electron Devices Meeting 2003

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