{"title":"基于90nm CMOS技术的15-20GHz延时锁相环","authors":"Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2008.4708766","DOIUrl":null,"url":null,"abstract":"A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 15–20GHz delay-locked loop in 90nm CMOS technology\",\"authors\":\"Jung-Yu Chang, Chi-Nan Chuang, Shen-Iuan Liu\",\"doi\":\"10.1109/ASSCC.2008.4708766\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708766\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 15–20GHz delay-locked loop in 90nm CMOS technology
A 15 GHz~20 GHz delay-locked loop (DLL) has been fabricated in 90 nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20 GHz, the measured root-mean-square and peak-to-peak jitters are 0.813 ps and 6.62 ps, respectively. The core area is 0.25times0.4 mm2 and the power consumption is 49 mW for 0.9 V supply.
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