S. Chaitra, R. Shruthi, S. R. Shreyas, Shashidhara H R
{"title":"同步与异步NoC路由器的设计与实现","authors":"S. Chaitra, R. Shruthi, S. R. Shreyas, Shashidhara H R","doi":"10.1109/DISCOVER55800.2022.9974626","DOIUrl":null,"url":null,"abstract":"The System on chip (SoC) has been used widely in current chip development. Network-on-Chip (NoC) concepts are used to communicate between more numbers of devices in SoC that are being positioned on a single chip. This provides the way for an energy-efficient, cost, and reliable design. This paper proposes a simple synchronous NoC router and Argo asynchronous NoC router with low complexity and good performance for effective communication within the SoC. The high speed and low latency are achieved by providing a routing function for each input port with HPU blocks to decode the routing information and forward this to XBAR which in turn gives a high level of parallelism and guides the information to reach the proper destination. The proposed system verifies the effectiveness of the parameters like maximum fan-out, maximum frequency, and ALMs. The results obtained shows that there is a significant decrease in the maximum fan-out, maximum frequency and increase in ALMs for asynchronous router in comparison with synchronous router.","PeriodicalId":264177,"journal":{"name":"2022 International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics ( DISCOVER)","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The Design and Implementation of Synchronous and Asynchronous NoC Router\",\"authors\":\"S. Chaitra, R. Shruthi, S. R. Shreyas, Shashidhara H R\",\"doi\":\"10.1109/DISCOVER55800.2022.9974626\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The System on chip (SoC) has been used widely in current chip development. Network-on-Chip (NoC) concepts are used to communicate between more numbers of devices in SoC that are being positioned on a single chip. This provides the way for an energy-efficient, cost, and reliable design. This paper proposes a simple synchronous NoC router and Argo asynchronous NoC router with low complexity and good performance for effective communication within the SoC. The high speed and low latency are achieved by providing a routing function for each input port with HPU blocks to decode the routing information and forward this to XBAR which in turn gives a high level of parallelism and guides the information to reach the proper destination. The proposed system verifies the effectiveness of the parameters like maximum fan-out, maximum frequency, and ALMs. The results obtained shows that there is a significant decrease in the maximum fan-out, maximum frequency and increase in ALMs for asynchronous router in comparison with synchronous router.\",\"PeriodicalId\":264177,\"journal\":{\"name\":\"2022 International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics ( DISCOVER)\",\"volume\":\"1 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics ( DISCOVER)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DISCOVER55800.2022.9974626\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics ( DISCOVER)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DISCOVER55800.2022.9974626","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Design and Implementation of Synchronous and Asynchronous NoC Router
The System on chip (SoC) has been used widely in current chip development. Network-on-Chip (NoC) concepts are used to communicate between more numbers of devices in SoC that are being positioned on a single chip. This provides the way for an energy-efficient, cost, and reliable design. This paper proposes a simple synchronous NoC router and Argo asynchronous NoC router with low complexity and good performance for effective communication within the SoC. The high speed and low latency are achieved by providing a routing function for each input port with HPU blocks to decode the routing information and forward this to XBAR which in turn gives a high level of parallelism and guides the information to reach the proper destination. The proposed system verifies the effectiveness of the parameters like maximum fan-out, maximum frequency, and ALMs. The results obtained shows that there is a significant decrease in the maximum fan-out, maximum frequency and increase in ALMs for asynchronous router in comparison with synchronous router.