{"title":"可靠控制器的验证与实现","authors":"K. Sacha","doi":"10.1109/DepCoS-RELCOMEX.2008.30","DOIUrl":null,"url":null,"abstract":"A method is described for modeling, verification and automatic generation of code for PLC controllers. The modeling of requirements and the implementation of code are based on a definition of a finite state time machine. The verification process uses UPPAAL, a model checking tool for the networks of timed automata. A conversion between both models is done automatically. The method starts from modeling the desired behavior of the controller by means of an UML- based state machine diagram, and ends-up with a complete program in one of the IEC 1131 languages.","PeriodicalId":167937,"journal":{"name":"2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Verification and Implementation of Dependable Controllers\",\"authors\":\"K. Sacha\",\"doi\":\"10.1109/DepCoS-RELCOMEX.2008.30\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A method is described for modeling, verification and automatic generation of code for PLC controllers. The modeling of requirements and the implementation of code are based on a definition of a finite state time machine. The verification process uses UPPAAL, a model checking tool for the networks of timed automata. A conversion between both models is done automatically. The method starts from modeling the desired behavior of the controller by means of an UML- based state machine diagram, and ends-up with a complete program in one of the IEC 1131 languages.\",\"PeriodicalId\":167937,\"journal\":{\"name\":\"2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DepCoS-RELCOMEX.2008.30\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DepCoS-RELCOMEX.2008.30","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Verification and Implementation of Dependable Controllers
A method is described for modeling, verification and automatic generation of code for PLC controllers. The modeling of requirements and the implementation of code are based on a definition of a finite state time machine. The verification process uses UPPAAL, a model checking tool for the networks of timed automata. A conversion between both models is done automatically. The method starts from modeling the desired behavior of the controller by means of an UML- based state machine diagram, and ends-up with a complete program in one of the IEC 1131 languages.