单片式 3D BEOL FinFET 电路的位置控制纹理技术

2018 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2018-12-01 DOI:10.1109/IEDM.2018.8614708

Chih-Chao Yang, Tung-Ying Hsieh, Po-Tsang Huang, Kuan-Neng Chen, Wan-Chi Wu, Shih-Wei Chen, Chia-He Chang, C. Shen, J. Shieh, C. Hu, Meng-Chyi Wu, W. Yeh

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引用次数: 14

摘要

本文介绍了一种位置控制晶粒技术，用于在二氧化硅上制造 BEOL 单片 3D FinFET 集成电路。由此制造出的无晶粒边界硅 FinFET 具有陡峭的次阈值摆幅（385 美元/mathrm{A}/mathrm{m}$）和高离子/离子关断（>106）。根据模拟，层间电介质的厚度起着重要作用，其厚度应大于 250nm，以便顺序脉冲激光结晶过程不会将底部器件和互连器件加热到 400 °C 以上。

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Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO2. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 µA/µm and p-type: $385\ \mu \mathrm{A}/\mu \mathrm{m}$), and high Ion/Ioff (>10⁶). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

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2018 IEEE International Electron Devices Meeting (IEDM)

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