Shu-Xia Dong, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee
{"title":"双基乘法器在GF (2m)上的TMVP硬件实现","authors":"Shu-Xia Dong, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee","doi":"10.1109/ICAWST.2017.8256506","DOIUrl":null,"url":null,"abstract":"Finite field multiplication plays a important roles in the applications of elliptic curve cryptography. In this paper, we use PB and modified polynomial basis(MPB) define a double basis multiplication, where MPB is transformed by PB when F(x) = xm + xn + 1, n ≥. m/2 We find that the double multiplication can transformed into Toeplitz matrix vector produc-t(TMVP). To reduce time and space complexities, we recursively use two-way TMVP approach calculate the product of double basis multiplication. We respectively implement shifted addition algorithm and TMVP approach in hardware chip FPGA Kintex7-xc7k325T. The proposed structure can obtain significantly lower area-delay product.","PeriodicalId":378618,"journal":{"name":"2017 IEEE 8th International Conference on Awareness Science and Technology (iCAST)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Hardware implementation of double basis multiplier using TMVP approach over GF (2m)\",\"authors\":\"Shu-Xia Dong, Jeng-Shyang Pan, Chun-Sheng Yang, Chiou-Yng Lee\",\"doi\":\"10.1109/ICAWST.2017.8256506\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Finite field multiplication plays a important roles in the applications of elliptic curve cryptography. In this paper, we use PB and modified polynomial basis(MPB) define a double basis multiplication, where MPB is transformed by PB when F(x) = xm + xn + 1, n ≥. m/2 We find that the double multiplication can transformed into Toeplitz matrix vector produc-t(TMVP). To reduce time and space complexities, we recursively use two-way TMVP approach calculate the product of double basis multiplication. We respectively implement shifted addition algorithm and TMVP approach in hardware chip FPGA Kintex7-xc7k325T. The proposed structure can obtain significantly lower area-delay product.\",\"PeriodicalId\":378618,\"journal\":{\"name\":\"2017 IEEE 8th International Conference on Awareness Science and Technology (iCAST)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE 8th International Conference on Awareness Science and Technology (iCAST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAWST.2017.8256506\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 8th International Conference on Awareness Science and Technology (iCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAWST.2017.8256506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware implementation of double basis multiplier using TMVP approach over GF (2m)
Finite field multiplication plays a important roles in the applications of elliptic curve cryptography. In this paper, we use PB and modified polynomial basis(MPB) define a double basis multiplication, where MPB is transformed by PB when F(x) = xm + xn + 1, n ≥. m/2 We find that the double multiplication can transformed into Toeplitz matrix vector produc-t(TMVP). To reduce time and space complexities, we recursively use two-way TMVP approach calculate the product of double basis multiplication. We respectively implement shifted addition algorithm and TMVP approach in hardware chip FPGA Kintex7-xc7k325T. The proposed structure can obtain significantly lower area-delay product.