一种面向RISC-V处理器的区域优化浮点协处理器

2023 International Conference on Control, Communication and Computing (ICCC) Pub Date : 2023-05-19 DOI:10.1109/ICCC57789.2023.10165397

G. P, Jaya S, Krishnakumar Rao S

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引用次数: 0

摘要

本文概述了一种符合IEEE 754-2008标准的区域优化浮点单元(FPU)的设计与开发。该FPU作为基于RISC-V ISA的VEGA处理器的协处理器。FPU支持58条RISC-V浮点指令的有序和无序执行，并带有部分流水线。

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An Area Optimized Floating-Point Coprocessor for RISC-V Processor

In this paper, we outline the design and development of an area optimized Floating-Point Unit (FPU) in accordance with the IEEE 754-2008 standard. This FPU acts as a coprocessor for RISC-V ISA based VEGA processor. The FPU supports both in-order and out-of-order execution of 58 RISC-V floating-point instructions with partial pipelining.

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2023 International Conference on Control, Communication and Computing (ICCC)

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