{"title":"100纳米CMOS技术。设计视角","authors":"H. Veendrick","doi":"10.1109/TUTCAS.2001.946981","DOIUrl":null,"url":null,"abstract":"This article discusses the design of 100 nm CMOS integrated circuits, emphasising the implications for transistors, logic circuits, matching techniques and embedded systems. Included is a discussion of the requirements of high-speed low-power circuits, and the emerging system-on-chip technologies.","PeriodicalId":376181,"journal":{"name":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"100 nm CMOS technology. A design perspective\",\"authors\":\"H. Veendrick\",\"doi\":\"10.1109/TUTCAS.2001.946981\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article discusses the design of 100 nm CMOS integrated circuits, emphasising the implications for transistors, logic circuits, matching techniques and embedded systems. Included is a discussion of the requirements of high-speed low-power circuits, and the emerging system-on-chip technologies.\",\"PeriodicalId\":376181,\"journal\":{\"name\":\"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TUTCAS.2001.946981\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TUTCAS.2001.946981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This article discusses the design of 100 nm CMOS integrated circuits, emphasising the implications for transistors, logic circuits, matching techniques and embedded systems. Included is a discussion of the requirements of high-speed low-power circuits, and the emerging system-on-chip technologies.