{"title":"动态集群芯片多处理器","authors":"Chao-Chin Wu, Guan-Joe Lai","doi":"10.1109/PACRIM.2005.1517238","DOIUrl":null,"url":null,"abstract":"Chip multiprocessors (CMPs) can outperform superscalar processors only for the application programs with full of thread-level parallelism. In this paper, we investigate how to combine both the advantages of a CMP and of a superscalar to execute an application. We aggregate multiple processing elements (PEs) in the CMP into a wide superscalar processor. The number of aggregated PEs is dynamically determined by the dependence distance of subsequent thread at the run time. According to different aggregation methods, the new CMP is capable of supporting three execution modes. To obtain the best performance, the processor keeps switching between different execution modes when executing an application, according to the characteristics of subsequent instructions.","PeriodicalId":346880,"journal":{"name":"PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A dynamically clustered chip multiprocessor\",\"authors\":\"Chao-Chin Wu, Guan-Joe Lai\",\"doi\":\"10.1109/PACRIM.2005.1517238\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip multiprocessors (CMPs) can outperform superscalar processors only for the application programs with full of thread-level parallelism. In this paper, we investigate how to combine both the advantages of a CMP and of a superscalar to execute an application. We aggregate multiple processing elements (PEs) in the CMP into a wide superscalar processor. The number of aggregated PEs is dynamically determined by the dependence distance of subsequent thread at the run time. According to different aggregation methods, the new CMP is capable of supporting three execution modes. To obtain the best performance, the processor keeps switching between different execution modes when executing an application, according to the characteristics of subsequent instructions.\",\"PeriodicalId\":346880,\"journal\":{\"name\":\"PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005.\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACRIM.2005.1517238\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"PACRIM. 2005 IEEE Pacific Rim Conference on Communications, Computers and signal Processing, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.2005.1517238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Chip multiprocessors (CMPs) can outperform superscalar processors only for the application programs with full of thread-level parallelism. In this paper, we investigate how to combine both the advantages of a CMP and of a superscalar to execute an application. We aggregate multiple processing elements (PEs) in the CMP into a wide superscalar processor. The number of aggregated PEs is dynamically determined by the dependence distance of subsequent thread at the run time. According to different aggregation methods, the new CMP is capable of supporting three execution modes. To obtain the best performance, the processor keeps switching between different execution modes when executing an application, according to the characteristics of subsequent instructions.