根据系统规格自动生成测试过程

[1992 Proceedings] The Third International Workshop on Rapid System Prototyping Pub Date : 1992-06-23 DOI:10.1109/IWRSP.1992.243898

M. Lindsey

{"title":"根据系统规格自动生成测试过程","authors":"M. Lindsey","doi":"10.1109/IWRSP.1992.243898","DOIUrl":null,"url":null,"abstract":"Automated aids to generating test procedures for electronic systems from top-level system specifications are described. A five-phase design methodology which incorporates VHSIC description language, (VHDL) modeling allows concurrent development of complex systems and associated test procedures. The methodology proceeds in a top-down fashion, progressively adding design detail in each phase. A proprietary software tool combined with VHDL modeling allow test information to automatically migrate through each phase. This allows system implementation to be verified against the original top-level specification. This method of automated test procedure generation provides significant insight into system operation.<<ETX>>","PeriodicalId":210681,"journal":{"name":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Automatic test procedure generation from system specifications\",\"authors\":\"M. Lindsey\",\"doi\":\"10.1109/IWRSP.1992.243898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Automated aids to generating test procedures for electronic systems from top-level system specifications are described. A five-phase design methodology which incorporates VHSIC description language, (VHDL) modeling allows concurrent development of complex systems and associated test procedures. The methodology proceeds in a top-down fashion, progressively adding design detail in each phase. A proprietary software tool combined with VHDL modeling allow test information to automatically migrate through each phase. This allows system implementation to be verified against the original top-level specification. This method of automated test procedure generation provides significant insight into system operation.<<ETX>>\",\"PeriodicalId\":210681,\"journal\":{\"name\":\"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWRSP.1992.243898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992 Proceedings] The Third International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1992.243898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

描述了从顶层系统规范生成电子系统测试程序的自动化辅助工具。采用VHSIC描述语言(VHDL)建模的五阶段设计方法允许复杂系统和相关测试程序的并发开发。该方法以自顶向下的方式进行，在每个阶段逐步添加设计细节。与VHDL建模相结合的专有软件工具允许测试信息在每个阶段自动迁移。这允许根据原始的顶级规范来验证系统实现。这种自动测试过程生成的方法提供了对系统操作的重要洞察。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Automatic test procedure generation from system specifications

Automated aids to generating test procedures for electronic systems from top-level system specifications are described. A five-phase design methodology which incorporates VHSIC description language, (VHDL) modeling allows concurrent development of complex systems and associated test procedures. The methodology proceeds in a top-down fashion, progressively adding design detail in each phase. A proprietary software tool combined with VHDL modeling allow test information to automatically migrate through each phase. This allows system implementation to be verified against the original top-level specification. This method of automated test procedure generation provides significant insight into system operation.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

[1992 Proceedings] The Third International Workshop on Rapid System Prototyping

自引率

0.00%

发文量